AV143

Product overview

The AV143 is part of apissys’ range of High-Speed data conversion and signal processing solutions based on the VITA 46, VPX standard.

The AV143 is fully compliant with OpenVPX standard, accommodating various communication protocols such as PCIe, SRIO, 1 Gbit and XAUI 10 Gbit Ethernet, as well as non OpenVPX adopted standard such as Aurora.

The AV143 combines one dual channel 12-bit 3.2 Gsps / single channel 12-bit 6.4 Gsps ADC and one dual channel 12-bit 3.2 Gsps / single channel 12-bit 6.4 Gsps DAC with ultra-high processing power delivered by Xilinx® Virtex® Ultrascale+™ FPGA, making it ideally suited for embedded signal processing applications such as Electronic Warfare, Wideband Radar Transmitter/Receivers or Wideband Communication applications.

The AV143 features an internal ultra-low jitter reference and one clock synthesizer and can be used with either external clock or external reference for higher flexibility.

The AV143 includes one Xilinx® Virtex® Ultrascale+™ VU13P FPGA for an impressive processing capability of more than 19 TMACs (Multiply Accumulate per second), two 1G64 DDR4-2666 SDRAM memory for data processing and 2 Gb synchronous FLASH memory for multiple firmware storage. The AV143 can also be fitted with one Xilinx® Virtex® Ultrascale+™ VU7P or VU9P FPGA.

The AV143 provides a USB 2.0 interface and a USB to UART interfaces intended to be used for system monitoring and supervision.

The AV143 comes with complete software drivers for Windows and Linux. An FPGA Development Kit is provided including all necessary cores to build user FPGA application.

Benefits & features

  • Dual 3.2 Gsps / Single 6.4 Gsps 12-bit ADC
  • Dual 3.2 Gsps / Single 6.4 Gsps 12-bit DAC
  • One Ultra Low jitter clock synthesizer
  • External or internal sampling clock
  • External or internal sampling clock reference
  • User programmable Xilinx® Virtex® Ultrascale+™ VU7P/VU9P/VU13P FPGA
  • 2x 1G64 DDR4-2666 SDRAM
  • 3U OpenVPX standard compliant
  • Air cooled and Conduction cooled rugged versions

Description

12-bit 3.2/6.4 Gsps ADC
The AV143 Analog to Digital conversion is performed by one Texas Instruments ADC12DL3200 12-bit 3.2/6.4 Gsps ADC
The AV143 provides two front panel SMPM connectors for analog input.
Single ended input signals are AC coupled with an input bandwidth from 10 MHz to more than 8 GHz with TBD dBm input level.

12-bit 3.2/6.4 Gsps DAC
The AV143 Digital to Analog conversion is performed by one Texas Instruments DAC12DL3200 12-bit 3.2/6.4 Gsps DAC.
The AV143 provides two front panel SMPM connectors for analog output.
Single ended output signals are AC coupled with an output bandwidth from 10 MHz to more than 8 GHz with TBD dBm output level (NRZ).

Clock
The AV143 provides one ultra-low jitter clock synthesizer locked on a 100 MHz internal reference. The AV143 supports a 10 to 500 MHz external reference input from a front panel SMPM connector. A reference output is available on a front panel SMPM connector.
An external clock input for the ADC and DAC is supported from one front panel SMPM connector.
External clock frequencies from 1.6 GHz to 6.4 GHz are supported.

Trigger and Synchronization
The AV143 provides one front panel SMPM connector for external trigger input.

FPGA
The AV143 is fitted with a Xilinx® Virtex® Ultrascale+™ VU7P, VU9P or VU13P user programmable FPGA. Only few resources are used to control and communicate with external hardware such as DDR4 SDRAM and monitoring sub-system, leaving most of the logic and block RAM and all DSP resources available for customer processing.
Dedicated to signal processing, the Xilinx Virtex Ultrascale+ VU13P FPGA includes 3,780 K logics cells, 94.5 Mbit of RAM blocs, 360 Mbit of Ultra RAM, 4 PCIe GEN3x16 interface blocs and 12,288 DSP48 slices for an impressive processing power of more than 19 TMACs.
The FPGA is delivered in -2 speed grade.

Memories
The AV143 includes two 1G64 DDR4-2666 SDRAM memory banks and one 2 Gbit QSPI FLASH used to store multiple FPGA configuration files.

VPX interface
The AV143 features an OpenVPX VITA 65 compliant interface with support for two Fat Pipes for Data Plane, one Fat Pipe for Expansion Plane, two Ultra-Thin Pipes for Control Plane and two User Defined Ultra-Thin Pipes on P1. The AV143 also supports 22 LVDS differential pairs configurable as 44 single-ended LVCMOS on P2 plus USB2.0 and UART for supervision and monitoring.
The AV143 features one low phase noise clock generator able to synthesize clock references for the FPGA GTYs from 60 MHz to 820 MHz, allowing support of all major protocols such as Aurora, GigE, PCIe Gen 1, 2 and 3 and XAUI 10Gbit Ethernet up to 28 Gbps.

Microcontroller
The AV143 features a 32-bit 200 MHz microcontroller used primarily for board monitoring and supervision.
The microcontroller supports a USB 2.0 and a UART interfaces accessible on the VPX P2 user IO pins through an ApisSys AR113 Rear Transition Module.
The microcontroller firmware includes all necessary features for board monitoring and supervision.

Firmware
The AV143 comes with a firmware package which includes VHDL cores allowing for control and communication with all AV143 hardware resources.
A base design is provided which demonstrates the use of the AV143 and gives users a starting point for firmware development. The AV143 firmware package is supported on the Xilinx VIVADO® 2022.1 design suite.

Software
The AV143 is delivered with software drivers for Windows 10 and Linux.

Ruggedization
The AV143 is delivered in air cooled and conduction cooled standard or rugged versions for use in severe environmental conditions.
Standard VITA 47 ruggedization levels supported are EAC4, EAC6, ECC3 and ECC4.

Diagrams

Tech specs

Analog Inputs/Outputs

• Input coupling: AC
• Full power bandwidth: > 8 GHz
• Full scale : TBD dBm
• Output coupling: AC
• Full power bandwidth: > 8 GHz
• Full scale : TBD dBm (NRZ)
• Impedance: 50 Ohm
• Connectors: SMPM


Analog-Digital Conversion

• Dual channel, Fs ≤ 3.2 GHz
• Single channel, Fs ≤ 6.4 GHz
• Resolution: 12 bit
• Sampling Performances 6.4 Gsps, -1dBFS
• SNR: 55 dBFS @2.1 GHz
• SFDR: 60 dBc @2.1 GHz
• ENOB: 5 bit @2.1 GHz


Digital-Analog Conversion

• Dual channel, Fs ≤ 3.2 GHz
• Single channel, Fs ≤ 6.4 GHz
• Resolution: 12 bit
• Sampling Performances 6.4 Gsps, 0 dBFS
• SFDR: 67 dBc, NRZ mode @ 2.1 GHz
• NSD: -154 dBc/Hz, NRZ mode @ 2.1 GHz


Clock

• Internal:
• One ultra-low jitter clock synthesizers
• 6 GHz to 6.4 GHz low jitter clock
• External Input Clock:
• Frequency: 1.6 GHz to 6.4 GHz
• Input level: 10 dBm recommended
• Connector: SMPM 50 Ohms
• External reference:
• frequency: 10 MHz to 500 MHz
• Connector: SMPM, 50 Ohm

Trigger

• External: 0 to 2.5Vp
• Connector: SMPM, 50 Ohm


FPGA

• Xilinx Virtex Ultrascale+:
• XCVU7P-2FLVB2104I
• XCVU9P-2FLGB2104I
• XCVU13P-2FHGB2104I


Memory

• Two banks 1G64 DDR4 2666 SDRAM
• One 2 Gbit QSPI FLASH memory


VPX interface

• P1:
• Data plane: two fat pipes
• Expansion plane: one fat pipe
• Control plane: 2 ultra-thin pipes
• 2 user-defined ultra-thin pipes
• P2:
• 0 and USB to UART
• 22 LVDS differential pairs, configurable as 44 single ended LVCMOS

Software support

• Software Drivers
• Windows 10 64-bits
• Linux 64-bits


Firmware support

• VHDL cores for all hardware resources
• Base design
• Supported by Xilinx VIVADO 2022.1</div


Ruggedization

• As per VITA 47:
• Air cooled: EAC4 and EAC6
• Conduction cooled: ECC3 and ECC4


Power dissipation (VU13P)

• +12V: 11.4 A max (137W)
• +3.3VAUX: 0.6 A max (2W)


Weight

• Air cooled : 550g
• Conduction cooled : 650g

Deliverables

Part Number A V 143 - rr - a
Ruggedization level Air Standard
Air Rugged
Conduction Standard
Conduction Rugged
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AS
AR
CS
CR
-
-
-
-
-
-
-
-
Options FPGA Virtex Ultrascale+ VU7P
FPGA Virtex Ultrascale+ VU9P
FPGA Virtex Ultrascale+ VU13P
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
7
9
13

Applications

  • Electronic Warfare – Electronic Attack
  • DRFM
  • Radar Transmitter / Receiver
  • Wideband Communication

ruggedization

Air flow, Standard
AS (VITA 47 EAC4)
Air flow, Rugged
AR (VITA 47 EAC6)
Conduction Standard
CS (VITA 47 ECC3)
Conduction Rugged
CR (VITA47 ECC4)
Operating
Temperature
0°C to +55°C (1)
(10 CFM airflow at sea level)
-40 to +70ºC (1)
(20 CFM airflow at sea level)
-40°C to +70°C
(Card Edge)
-40°C to +85°C
(Card Edge)
Non Operating Temperature -40°C to +85°C -50°C to +100°C -50°C to +100°C -55°C to +105°C
Operating
Vibration
(Random)
5Hz - 100Hz +3 dB/octave
100Hz-1kHz = 0.04 g2/Hz
1kHz - 2kHz -6 dB/octave
5Hz - 100Hz +3 dB/octave
100Hz - 1kHz = 0.04 g2/Hz
1kHz - 2kHz -6 dB/octave
5Hz - 100Hz +3 dB/octave
100Hz - 1kHz = 0.1 g2/Hz
1kHz - 2kHz -6 dB/octave
5Hz - 100Hz +3 dB/octave
100Hz - 1kHz = 0.1 g2/Hz
1kHz - 2kHz -6 dB/octave
Operating Shock 20g, 11 millisecond, half-sine 20g, 11 millisecond, half-sine 40g, 11 millisecond, half-sine 40g, 11 millisecond, half-sine
Operating
Relative Humidity
0% to 95%
non-condensing
0% to 95%
non-condensing
0% to 95%
non-condensing
0% to 95%
non-condensing
Operating
Altitude
@ 0 to 10,000 ft
with adequate airflow
@ 0 to 30,000 ft
with adequate airflow
@ 0 to 30,000 ft @ 0 to 60,000 ft
Conformal Coating No Optional (default acrylic AVR80) Yes (default acrylic AVR80) Yes (default acrylic AVR80)

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