AF207

Product overview

Arbitrary Broadband Signal Generation L and S bands, Automatic Test Equipment (ATE)

The AF207 is part of ApisSys’ range of modular IOs solutions based on the VITA 57, FPGA Mezzanine Card standard.

The AF207 provides customers with a dual channel 14-bit up to 2.8 Gsps DAC capability, ideally suited for test and measurement, Software Defined Radio or Radar Transmitter applications.

The AF207 DAC channels are AC coupled with an output bandwidth wider than 5 GHz for a full scale signal of -4 dBm (400 mVpp).

The AF207 provides an internal ultra-low jitter clock generation and can be used with either an external clock or an external reference for higher flexibility.

The AF207 features an external trigger input and an external trigger output used to synchronize processing with external events.

The AF207 is fully supported on ApisSys 3U VPX FPGA processing engines.

Benefits & features

Description

Diagrams

Tech specs

Deliverables

Applications

Ruggedization

Benefits & features

Single Slot FMC HPC
2 channels 14-bit, 2.8 Gsps DAC
External clock and reference input
Internal low jitter clock generation
External trigger input and output
VITA 57 FMC form factor
Air cooled and Conduction cooled rugged versions
FPGA firmware cores

Description

14-bit 2.8 GSPS DACs
The AF2074 Digital to Analog conversion is performed by two Analog Devices AD9129 14-bit 2.8 Gsps DAC.The DACs can be used with x2 interpolator for improved performances with 5.6 Gsps DAC update rate.The AF207 provides two front panel SSMC connectors for the analog outputs.The output signal is single ended AC coupled with an output bandwidth from 1 MHz to more than 5 GHz with -4 dBm output level.

Clock
The AF207 provides an internal ultra low jitter clock generator locked on a 100 MHz internal reference.The AF207 provides a front panel SSMC connector for an external reference from 10 to 100 MHz, a front panel SSMC connector for an external clock input from 500 MHz to 2.8 GHz.Estimated jitter from the internal clock generation (including 100 MHz reference and clock distribution) is below 200 fs for a 2.8 GHz clock. Added jitter on external clock is lower than 100 fs.

Trigger and Synchronization
The AF207 provides a front panel SSMC connector for an external trigger input and one front panel SSMC connector for an external trigger output.The trigger input and output signals are buffered with ultrafast PECL buffers.

FMC interface
The AF207 features a VITA 57 – FMC (FPGA Mezzanine Card) compliant interface.The FMC uses High Pin Count (HPC) interface with 1.8V or 2.5V Vadj.The FMC MGT interfaces are unused.

Firmware
The AF207 comes with a firmware package which includes VHDL cores allowing control and communication with all AF207 hardware resources.A base design is provided which demonstrates the use of the AF207 and gives users a starting point for firmware development.The AF207 firmware package is supported on the Xilinx ISE® 14 and VIVADO 2014.2 design suites and later versions.The AF207 firmware package has been fully validated on AV108 and other ApisSys FMC carrier products.

Software
The AF207 is delivered with a control software compatible with AV108 and other ApisSys FMC carrier products.An application example is provided as source code.

Ruggedization
The AF207 is delivered in air cooled and conduction cooled standard or rugged versions for use in severe environmental conditions.Standard VITA 47 supported ruggedization levels are EAC4, EAC6 and ECC3.

Diagrams

Tech specs

Analog Output

• Output coupling: AC
• Full power bandwidth > 5.0 GHz
• Full scale : -4 dBm
• Impedance: 50 Ohm
• Connector: SSMC

Digital to Analog Conversion

• Dual channel
• Resolution: 14 bit
• Sampling Frequency 500 MHz to 2.8 GHz

Sampling Performances

• 2.8 Gsps, Fout = 800 MHz, -1dBFS, baseband:
• SFDR: 60 dBc
• Clock spur: -85 dBc (Fc/2)
• 2.8 Gsps, Fout = 1.6 GHz, -1dBFS, mix-mode:
• Noise Density : -154 dBm/Hz
• SFDR: 59 dBc
• Clock spur : -81 dBc (Fc/2)
• Clock spur : -55 dBc (Fc)
• 2.8 Gsps, Fout = 2.5 GHz, -1dBFS, RF:
• Noise Density : -152 dBm/Hz
• SFDR: 67 dBc

Trigger

• External trigger Input
• External Input: 0V to 2Vp
• Connector: SSMC, 50 Ohms
• External trigger Output
• External Output: 0V to 2Vp
• Connector: SSMC, 50 Ohms

Clock

• Internal low jitter clock (assembly option):
• 500 MHz to 2.8 GHz
• Internal jitter: < 200 fs
• External Input Clock:
• Frequency: 500 MHz to 2.8 GHz
• Level: 10 dBm to 15 dBm
• Added jitter (Ext clock) < 100 fs
• Connector: SSMC, 50 Ohms
• External reference:
• Frequency: 10 MHz to 100 MHz
• Level: 10 dBm to 15 dBm
• Connector: SMC, 50 Ohms

FMC interface

• HPC:
• LA(0:33): LVDS 1.8V or 2.5V
• HA(0:23): LVDS 1.8V or 2.5V
• HB(0:21): LVCMOS 1.8V or 2.5V

Software support

• Software and Application example
• Windows and Linux

Firmware support

• VHDL cores for all hardware resources
• Base design
• Supported by Xilinx ISE 14, VIVADO 2014.2 and later

Ruggedization

• As per VITA 47:
• Air cooled : EAC4 and EAC6
• Conduction cooled : ECC3

Power dissipation

• +12V: 0.3 A max (4.0W)
• +3.3V: < 1.3 A (4.2W)
• VADJ (1.8V or 2.5V): 0.1 A max (0.3W)
• +3.3VAUX: < 0.1 A (0.4W)

Weight

• Air cooled : 50g
• Conduction cooled : 55g

Deliverables

Part Number		A	F	207	-	rr	-	a
Ruggedization level	Air Standard Air Rugged Conduction Standard	- - -	- - -	- - -	- - -	AS AR CS	- - -	- - -

Applications

Radar Emitter-Receiver
Physics
Data Communication

ruggedization

	Air flow, Standard AS (VITA 47 EAC4)*	Air flow, Rugged AR (VITA 47 EAC6)*	Conduction Standard CS (VITA 47 ECC3)*
Operating Temperature	0°C to +55°C (1) (8 CFM airfl ow at sea level)	-40 to +70ºC (1) (8 CFM airfl ow at sea level)	-40°C to +70°C (Card Edge)
Non Operating Temperature	-40°C to +85°C	-50°C to +100°C	-50°C to +100°C
Operating Vibration (Random)	5Hz - 100Hz +3 dB/octave 100Hz-1kHz = 0.04 g2/Hz 1kHz - 2kHz -6 dB/octave	5Hz - 100Hz +3 dB/octave 100Hz - 1kHz = 0.04 g2/Hz 1kHz - 2kHz -6 dB/octave	5Hz - 100Hz +3 dB/octave 100Hz - 1kHz = 0.1 g2/Hz 1kHz - 2kHz -6 dB/octave
Operating Shock	20g, 11 millisecond, half-sine	20g, 11 millisecond, half-sine	40g, 11 millisecond, half-sine
Operating Relative Humidity	0% to 95% non-condensing	0% to 95% non-condensing	0% to 95% non-condensing
Operating Altitude	@ 0 to 10,000 ft with adequate airflow	@ 0 to 30,000 ft with adequate airflow	@ 0 to 30,000 ft
Conformal Coating	No	Optional (acrylic AVR80)	Yes (default acrylic AVR80)

*Reference to ANSI-VITA standard VITA 47 (r2) for the listed parameters only. Temperature cycling or other not listed VITA 47 requirements on demand

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