AV127

Description

Optical Links Interfaces
The AV127 supports up to three x12 Optical Links Transmitters and three x12 Optical Links Receivers.The Optical Links Transmitters and Receivers support up to 14 Gbps on commercial temperature grade (0°C to +55°C) and up to 10 Gbps on industrial temperature grade (-40°C to +85°C). The Optical links use a proven 850 nm VCSEL array technology.The AV127 supports three MTP (MPO) adapters on the front panel supporting x24 MT ferules.

Clock Synthesizers
The AV127 provides one low jitter clock synthesizers for each x12 Optical Links transceiver block.Each clock synthesizer can synthesize two clock references for the FPGA GTHs from 60 MHz to 820 MHz locked on a common 25 MHz, allowing support of all major protocols such as Aurora, GigE, PCIe Gen 1 and Gen 2, SATA, SRIO and XAUI 10Gbit Ethernet up to 14 Gbps.

FPGA
The AV127 is fitted with a Xilinx® Kintex® Ultrascale™ KU115 user programmable FPGA. Only few resources are used to control and communicate with external hardware such as DDR3 SDRAM and monitoring sub-system, leaving most of the logic and block RAM and all DSP resources available for customer processing.Dedicated to signal processing, the Xilinx Kintex Ultrascale KU115 FPGA includes 1,451 K logics cells, 2,160 36 Kbit RAM blocs, 6 PCIe interface blocs and 5,520 DSP48 slices for an impressive processing power of more than 7 TMACs.The FPGA is delivered in -2 speed grade.

Memories
The AV127 includes two 800 MHz 256M64 DDR3 SDRAM memory banks and two 1 Gbit QSPI FLASH used to store multiple FPGA configuration files.A dual banks 512M64 is available on demand for -AS only version

VPX interface
The AV127 features an OpenVPX VITA 65 compliant interface with support for two Fat Pipes for Data Plane, one Fat Pipe for Expansion Plane, two Ultra-Thin Pipes for Control Plane and two User Defined Ultra-Thin Pipes on P1. The AV127 also supports 28 LVCMOS33 signals and 4 SUB-LVDS differential pairs on P2 plus USB2.0 and 10/100 Ethernet for supervision and monitoring.The AV127 features two low phase noise clock generators able to synthesize clock references for the FPGA GTHs from 60 MHz to 820 MHz, allowing support of all major protocols such as Aurora, GigE, PCIe Gen 1, 2 and 3, SATA, SRIO and XAUI 10Gbit Ethernet up to 16.375 Gbps.

Microcontroller
The AV127 features a 32-bit 80 MHz microcontroller used primarily for board monitoring and supervision.The microcontroller supports a USB 2.0 and a 10/100 Ethernet interfaces accessible on the VPX P2 user IO pins through an ApisSys AR102 Rear Transition Module or an ANSI/VITA 46.10 compliant custom RTM board.The microcontroller firmware includes all necessary features for board monitoring and supervision.

Firmware
The AV127 comes with a firmware package which includes VHDL cores allowing for control and communication with all AV127 hardware resources.A base design is provided which demonstrates the use of the AV127 and gives users a starting point for firmware development. The AV127 firmware package is supported on the Xilinx VIVADO® 2017.4 design suite and later.

Software
The AV127 is delivered with software drivers for Windows 10 and Linux.

Ruggedization
The AV127 is delivered in air cooled and conduction cooled standard or rugged versions for use in severe environmental conditions.Standard VITA 47 supported ruggedization levels are EAC4, EAC6, ECC3 and ECC4.

Diagrams

Tech specs

Deliverables

Applications

• EW SDR-COMINT
• Radar Emitter-Receiver
• Physics
• EW ESM-RWR
• Data Communication

ruggedization