AV145

Description

14-bit 5 Gsps ADCs
The AV145 supports eight Analog to Digital conversion channels from the RFSoC GEN 3 device with up to 14-bit 5 Gsps conversion rate.
The AV145 provides eight front panel SMPM connectors for analog inputs.
Single ended input signals are AC coupled with an input bandwidth from 10 MHz to more than 6 GHz with 8 dBm input level.

14-bit 9.85 Gsps DACs
The AV145 supports eight Digital to Analog conversion channels from the RFSoC GEN 3 device with up to 14-bit 9.85 Gsps conversion rate.
The AV145 provides eight front panel SMPM connectors for analog outputs.
Single ended output signals are AC coupled with an ouput bandwidth from 10 MHz to more than 6 GHz with -3 dBm output level.

Clock
The AV145 provides one ultra-low jitter clock synthesizer for the ADC channels and one ultra-low jitter clock synthesizer for the DAC channels, both locked on a common 100 MHz internal reference or on the external reference.
The AV145 supports a 10 to 200 MHz external reference input either from a front panel SMPM connector or from the VPX P2 Connector. A reference output is available on a front panel SMPM connector and on VPX P2.

RFSoC
The AV145 is fitted with a Xilinx® ZYNQ® Ultrascale+™ GEN3 XCZU47DR user programmable RFSoC. Only few resources are used to control and communicate with external hardware such as VPX Interface or clock synthesizers, leaving most of the logic, block RAM, Ultra RAM and all DSP resources available for customer processing.
Dedicated to signal processing, the Xilinx ZYNQ Ultrascale+ XCZU47DR RFSoC include 930 K logics cells, 38 Mbit of RAM blocs, 22.5 Mbit of Ultra RAM, 2 PCIe GEN3x16 interface blocs and 4,272 DSP48 slices for an impressive processing
power of more than 5.5 TMACs.
The RFSoC is delivered in -2 speed grade.

VPX interface
The AV145 features an OpenVPX VITA 65 compliant interface with support for two Fat Pipes for Data Plane connected to the RFSoC Programmable Logic.
The AV145 also supports one GbE interface configurable as 1000BASE-T or 1000BASE-BX, one UART and one USB2.0 interfaces connected to the RFSoC Processing System.
The AV145 features 18 LVDS differential pairs configurable as 36 single-ended LVCMOS on P2.
The AV145 features one low phase noise clock generator able to synthesize clock references for the RFSoC GTRs and GTYs, allowing support of all major protocols such as Aurora, GigE, PCIe Gen 1, 2 and 3, SATA, SRIO and XAUI 10Gbit Ethernet up to 25.785 Gbps

Memories
The AV145 includes one 512M64, with support for up to 1G64, DDR4-2400 SDRAM memory bank connected to the RFSoC Processing System.
The AV145 features two 2 Gbit QSPI FLASH memories used to store the RFSoC boot files and Programmable Logic configuration files.
A 512GB or 1TB NVMe SSD is connected to the RFSoC Processing System embedded PCIe interface for data storage.

Software and Firmware
The AV145 is delivered with a Linux distribution for the Arm Cortex-A53 cores.
The AV145 comes with a firmware package which includes VHDL cores allowing for control and communication with all AV145 hardware resources.
A base design is provided which demonstrates the use of the AV145 and gives users a starting point for firmware development. The AV145 firmware package is supported on the Xilinx VIVADO^® (version TBD) design suite.

Software
The AV145 is delivered with a Linux BSP.

Ruggedization
The AV145 is delivered in air cooled and conduction cooled standard or rugged versions for use in severe environmental conditions.
Standard VITA 47 supported ruggedization levels are EAC4, EAC6 and ECC4

Diagrams

Tech specs

Deliverables

ECCN

ECCN number: 3A002h1

Applications

• Electronic Warfare – Radar-ESM - ECM
• Wideband Radar Transmitter / Receiver
• MIMO
• Wideband Communication

ruggedization